Various electronic design automation (EDA) associated with semiconductor design automation are increasingly supplied and design methods using hardware description language (HDL) become universal in nowadays, which has significantly improved the design environment of application specific integrated circuit (ASIC).
The size of the circuit to be designed has thus reached the level of designing a capacity in a range of several millions to tens of millions of gates in recent years from the conventional level of tens of thousands to hundreds of thousands, so that the ASIC may be implemented on one chip. A system having the above-described configuration is referred to as a System-on-a-chip (SoC).
In addition, when the ASIC or the SoC is designed, it is more general that some function blocks of an existing design may be modified or added rather than that a zero-based design for the whole part is developed, and the function blocks to be modified or added are also utilized such that intellectual property (IP) blocks present on a unit function block basis are utilized, which may be regarded as the general tendency of the ASIC or the SoC design in the recent years.
The IPs which provide such various applications and are provided as pre-designed models may be broadly classified as software IP and hardware IP.
The software IP is implemented as a language such as C, C++, system C, HDL, VERILOG® HDL (VHDL), etc. depending on a coding format of a source code, and the hardware IP is implemented as an ASIC, a Field Programmable Gate Array (FPGA), or a board, etc. which has mounted various devices including the same.